Batboard

I am trying to disable the CDM1250 transmit PL during link ID to prevent IDs from keying up the main repeater. The CDM allows programming an accessory pin to inhibit TX PL. The ID-o-Matic 3 ID board has a pin that goes high only when an ID is being sent. I tried Data PTT =L to the CWID KEY and TX PL INHIB=H to the CWID high-during-ID point. When the CWID transmits ID, the CDM goes into transmit, but ignores the H signal to disable TX PL. It seems to be an issue with the timing of the PTT and PL inhib, as the PL Inhib needs to be there before the PTT(?). Unknown if there is a time interval of ??? mS between PL Inhib and PTT.
The same thing happened when I tried to use the CWID ID signal to channel steer from the Ch1 PL to Ch2 no-PL channels. Again what looks to be a timing issue. I have an experiment running to look deeper into timing by running TX PL INHIB straight to the CDM, and delaying PTT from the CWID board with a CD4011 IC gate with variable delay pot. I'll post what I find.
Has anyone run into this timing issue with the CDMs?
Thanks and 73,
Duane KA1LM

Update:
I have been trying to get my link CDM1250 transmitter to drop PL transmit when its CWID occurs. I use a ID-O-Matic CWID and tried to run CWID PTT to the radio and the IDOM A3 pad that goes to 5V during ID, to the pin 6 TX PL INHIB function. No good! Also not good if I set Chan 1 as PL transmit and Chan 2 as no-PL, and have the IDOM A3 pin select chan 2 during the ID.
I rigged up a test board with a CD4011 IC as a 0-500 mS delay generator. A manual switch puts +5V on the CDM pin 6 command pin, and starts the delay generator to hold off the CDM DATA PTT from 0-500mS after the pin 6 goes active.
My CDM1250 reliably requires 40 mS MINIMUM PTT delay AFTER the pin 6 command is toggled.

Pin 6= TX PL INHIB: CDM DATA PTT <40 mS after pin 6 goes H, command ignored

Pin 6= CHAN SELECT (channel steering): CDM DATA PTT <40 mS after pin 6 goes H, LCD shows channel change, but radio speaker has error tone and no PTT.

SO.....the CDM1250 requires DATA PTT to be delayed >40 mS after the pin 6, etc function signal occurs.

Also noted: the ID-O-Matic CWID board has a built-in 250 mS delay of the CWID tone and A3 "High while ID" signal after it asserts transmit PTT.
Trying to use the A3 pin to inhibit the TX PL will not be practical as there would have to be a 250mS + 40 mS delay of the CDM pin 3 DATA PTT to have the A3 pin control the pin 6 TX PL INHIB function.

Logic needs to be pin 6 TX PL INHIB=H ...IF...CWID board PTT out is there with no link receiver COR (no user talking).
DATA PTT=L after 50 mS IF CWID keys AND link receiver is squelched.

That was an interesting finding!
73,
Duane KA1LM